Relation between Plasma Process-Induced Oxide Failure Fraction and Antenna Ratio

Conventional antenna charging theory predicts that the net current drawn from plasma is proportional to the charge collecting area of the antenna. However, a quantitative relation between plasma process-induced oxide failure fraction and antenna ratio (AR) has not been found yet. In this paper, yield data of antenna testers have been correlated to the AR in a 0.18 ¿m CMOS technology process. A model is built which fits the experiment data very well. Based on this model, yield loss data obtained on large AR test structures can be used to extrapolate the charging currents and yield loss of smaller AR structures which occur more often in real circuit

Low-Pressure CVD of Germanium-Silicon films using Silane and Germane sources

In this work a study of Low Pressure Chemical Vapour Deposition (LPCVD) of Germanium-Silicon films has been carried out. The films were deposited on thermally oxidised silicon wafers using a horizontal hot-wall LPCVD system, at deposition temperatures ranging from 430 to 480 oC and total pressures from 3 to 200 Pa. Pure GeH4 and SiH4 gas sources were used for the experiments. Growth kinetics and texture of GexSi1-x films versus varying deposition conditions, resulting in different film properties, were investigated. The effect of Germanium content in the layers on deposition rate at 430 oC and the change in the film crystallinity caused by deposition at different deposition pressures were studied

Adapting to a changing highschool population

This paper reports the recent changes in the EE Bachelor program at the University of Twente. Recent generations of freshman students exhibited a lack in mathematics skills and the ability to grasp the physics behind the equations. By starting of the curriculum with a new course “Introduction to electronics and electrical engineering (IEEE)�? we have managed to solve the issue of lacking entry levels while simultaneously eliminating the unmotivated or under skilled students in a very early stage in their studies

Modeling of the Reservoir Effect on Electromigration Lifetime

Electromigration behaviour in W-plug/metal stripe structures is different from conventional metal-strip structures because there is a blocking boundary formed by the immobile W-plug in the contact/via. Electromigration failures occur more readily close to the W-plug than in metal-strip structures because metal ions are forced away from the contacts/vias by electric current, blocking the contacts/vias area. Several works have reported electromigration lifetime of multiple level interconnects to be influenced by the presence of a reservoir around the contacts/vias. Reservoirs are metal parts that are not or are hardly conducting current that act as a source to provide atoms for the area around the blocking boundary where the atoms migrate away due to the electric current. Interconnect lifetime can be prolonged by using the reservoirs, called the ¿reservoir effect¿. 2D simulation of the effects of reservoirs has been performed. The stress build-up during electromigration in the contact area can be simulated for several configurations, separating the effects of overlap, total reservoir area, the reservoir layout directions (vertical and horizontal), number of contacts/vias and contact/via placement. It is very useful for IC design rules to estimate which parameters are important for IC reliability. In this study, we considered the critical stress that the metal line can sustain before void formation as failure criterion. The failure time is determined by the time to reach the critical stres

1/f noise and switched bias noise measurement in p-MOSFET with varying gate oxide thickness

MOS transistors are notorious for their low frequency noise, which increases with decreasing device size. Using a new noise measurement set up, the power spectral density of 1/f noise in MOSFETs decreases, if the transistors are switched “off��? periodically (switched bias conditions)[1]. In this work, noise measurements on p-MOSFET are reported, with gate oxide thickness varying from 2 to 20 nm, keeping the electric field in the channel constant at 1.4 MV/cm. The switched bias noise and the reduction in the switched bias noise for p-MOSFET, are investigated as a function of the gate oxide thickness and the switching amplitude. Recently reported literature[2] on explanation for switched biased noise reduction is then compared with our measurement results and some explanations are proposed

Deep reactive ion etching of in situ boron doped LPCVD Ge_0.7Si_0.3 using SF₆ and O₂ plasma

This paper reports on deep reactive ion etching (DRIE) of in situ highly boron doped low pressure chemical vapor deposited Ge0.7Si0.3 alloy in SF6 and O2 plasma. The effect of RF power, SF6 flow, O2 flow and temperature on the etch rate of Ge0.7Si0.3 films with a boron concentration of 2.1 × 1021 atoms/cm3 is investigated. Optimized conditions for a combination of a vertical etch profile and a high selectivity towards PECVD oxide are reported. The effect of boron doping concentration on the etch rate is also investigated. The etch rate is found to decrease with an increase in the dopant concentration. The developed SF6 and O2 based DRIE recipes are applied to fabricate GeSi microresonators

Impact of hot-carrier degradation on the low-frequency noise in MOSFETs under steady-state and periodic large-signal excitation

This letter reports the diagnostic power of the low-frequency noise analysis (steady-state and periodic large-signal excitation) in MOSFETs subjected to hot-carrier degradation. The LF noise under periodic large-signal excitation is shown to increase more rapidly than the LF noise in steady-state. Moreover the improvement in the LF noise performance due to periodic large-signal excitation, observed for fresh devices, gradually diminishes as the devices are subjected to hot-carrier stress

Stress-Induced Leakage Current in p+ Poly MOS Capacitors with Poly-Si and Poly-Si0.7Ge0.3 Gate Material

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si0.7 Ge0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory device

High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 ¿m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent ¿on¿/¿off¿ currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitutio

Diffusion and electrical properties of Boron and Arsenic doped poly-Si and poly-GexSi1−x(x 0.3)Ge_xSi_1-x(x~0.3) as gate material for sub-0.25 µm complementary metal oxide semiconductor applications

In this paper the texture, morphology, diffusion and electrical (de‐) activation of dopants in polycrystalline GexSi1-x and Si have been studied in detail. For gate doping B+,BF2+ and As+ were used and thermal budgets were chosen to be compatible with deep submicron CMOS processes. Diffusion of dopants is different for GeSi alloys, B diffuses significantly more slowly and As has a much faster diffusion in GeSi. For B doped samples both electrical activation and mobility are higher compared to poly‐Si. Also for the first time, BF2+ data of doped layers are presented, these show the same trend as the B doped samples but with an overall higher sheet resistance. For arsenic doping, activation and mobility are lower compared to poly‐Si, resulting in a higher sheet resistance. The dopant deactivation due to long low temperature steps after the final activation anneal is also found to be quite different. Boron‐doped GeSi samples show considerable reduced deactivation whereas arsenic shows a higher deactivation rate. The electrical properties are interpreted in terms of different grain size, quality and properties of the grain boundaries, defects, dopant clustering, and segregation, and the solid solubility of the dopants